lo-qrupdate-proto.h File Reference

#include "octave-config.h"
#include "f77-fcn.h"

Go to the source code of this file.

Functions
F77_RET_T	F77_FUNC (cch1dn, CCH1DN)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T	F77_FUNC (cch1up, CCH1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T	F77_FUNC (cchdex, CCHDEX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T	F77_FUNC (cchinx, CCHINX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T	F77_FUNC (cchshx, CCHSHX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T	F77_FUNC (clu1up, CLU1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T	F77_FUNC (clup1up, CLUP1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T	F77_FUNC (cqr1up, CQR1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T	F77_FUNC (cqrdec, CQRDEC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T	F77_FUNC (cqrder, CQRDER)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T	F77_FUNC (cqrinc, CQRINC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T	F77_FUNC (cqrinr, CQRINR)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T	F77_FUNC (cqrshc, CQRSHC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T	F77_FUNC (dch1dn, DCH1DN)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T	F77_FUNC (dch1up, DCH1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T	F77_FUNC (dchdex, DCHDEX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T	F77_FUNC (dchinx, DCHINX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T	F77_FUNC (dchshx, DCHSHX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX *F77_RET_T	F77_FUNC (dlu1up, DLU1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT const F77_CMPLX const F77_CMPLX F77_CMPLX *F77_RET_T	F77_FUNC (dlup1up, DLUP1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T	F77_FUNC (dqr1up, DQR1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T	F77_FUNC (dqrdec, DQRDEC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T	F77_FUNC (dqrder, DQRDER)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T	F77_FUNC (dqrinc, DQRINC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T	F77_FUNC (dqrinr, DQRINR)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T	F77_FUNC (dqrshc, DQRSHC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T	F77_FUNC (sch1dn, SCH1DN)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T	F77_FUNC (sch1up, SCH1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T	F77_FUNC (schdex, SCHDEX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T	F77_FUNC (schinx, SCHINX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T	F77_FUNC (schshx, SCHSHX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T	F77_FUNC (slu1up, SLU1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT const F77_CMPLX const F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT const F77_DBLE const F77_DBLE F77_DBLE *F77_RET_T	F77_FUNC (slup1up, SLUP1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T	F77_FUNC (sqr1up, SQR1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T	F77_FUNC (sqrdec, SQRDEC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T	F77_FUNC (sqrder, SQRDER)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T	F77_FUNC (sqrinc, SQRINC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T	F77_FUNC (sqrinr, SQRINR)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T	F77_FUNC (sqrshc, SQRSHC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T	F77_FUNC (zch1dn, ZCH1DN)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T	F77_FUNC (zch1up, ZCH1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T	F77_FUNC (zchdex, ZCHDEX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T	F77_FUNC (zchinx, ZCHINX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T	F77_FUNC (zchshx, ZCHSHX)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T	F77_FUNC (zlu1up, ZLU1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT const F77_CMPLX const F77_CMPLX F77_CMPLX *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT const F77_DBLE const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT const F77_REAL const F77_REAL F77_REAL *F77_RET_T	F77_FUNC (zlup1up, ZLUP1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T	F77_FUNC (zqr1up, ZQR1UP)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T	F77_FUNC (zqrdec, ZQRDEC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T	F77_FUNC (zqrder, ZQRDER)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T	F77_FUNC (zqrinc, ZQRINC)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T	F77_FUNC (zqrinr, ZQRINR)(const F77_INT &
F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE *F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL *F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE *F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL *F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE *F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL *F77_RET_T	F77_FUNC (zqrshc, ZQRSHC)(const F77_INT &

Function Documentation

F77_FUNC() [1/52]

F77_RET_T F77_FUNC	(	cch1dn	,
		CCH1DN
	)		const &

F77_FUNC() [2/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_FUNC	(	cch1up	,
		CCH1UP
	)		const &

F77_FUNC() [3/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_FUNC	(	cchdex	,
		CCHDEX
	)		const &

F77_FUNC() [4/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_FUNC	(	cchinx	,
		CCHINX
	)		const &

F77_FUNC() [5/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_FUNC	(	cchshx	,
		CCHSHX
	)		const &

F77_FUNC() [6/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_FUNC	(	clu1up	,
		CLU1UP
	)		const &

F77_FUNC() [7/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T F77_FUNC	(	clup1up	,
		CLUP1UP
	)		const &

F77_FUNC() [8/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_FUNC	(	cqr1up	,
		CQR1UP
	)		const &

F77_FUNC() [9/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_FUNC	(	cqrdec	,
		CQRDEC
	)		const &

F77_FUNC() [10/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_FUNC	(	cqrder	,
		CQRDER
	)		const &

F77_FUNC() [11/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_FUNC	(	cqrinc	,
		CQRINC
	)		const &

F77_FUNC() [12/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_FUNC	(	cqrinr	,
		CQRINR
	)		const &

F77_FUNC() [13/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_FUNC	(	cqrshc	,
		CQRSHC
	)		const &

F77_FUNC() [14/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_FUNC	(	dch1dn	,
		DCH1DN
	)		const &

F77_FUNC() [15/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_FUNC	(	dch1up	,
		DCH1UP
	)		const &

F77_FUNC() [16/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_FUNC	(	dchdex	,
		DCHDEX
	)		const &

F77_FUNC() [17/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_FUNC	(	dchinx	,
		DCHINX
	)		const &

F77_FUNC() [18/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_FUNC	(	dchshx	,
		DCHSHX
	)		const &

F77_FUNC() [19/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX* F77_RET_T F77_FUNC	(	dlu1up	,
		DLU1UP
	)		const &

F77_FUNC() [20/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT const F77_CMPLX const F77_CMPLX F77_CMPLX* F77_RET_T F77_FUNC	(	dlup1up	,
		DLUP1UP
	)		const &

F77_FUNC() [21/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T F77_FUNC	(	dqr1up	,
		DQR1UP
	)		const &

F77_FUNC() [22/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_FUNC	(	dqrdec	,
		DQRDEC
	)		const &

F77_FUNC() [23/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_FUNC	(	dqrder	,
		DQRDER
	)		const &

F77_FUNC() [24/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T F77_FUNC	(	dqrinc	,
		DQRINC
	)		const &

F77_FUNC() [25/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T F77_FUNC	(	dqrinr	,
		DQRINR
	)		const &

F77_FUNC() [26/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_FUNC	(	dqrshc	,
		DQRSHC
	)		const &

F77_FUNC() [27/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_FUNC	(	sch1dn	,
		SCH1DN
	)		const &

F77_FUNC() [28/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_FUNC	(	sch1up	,
		SCH1UP
	)		const &

F77_FUNC() [29/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_FUNC	(	schdex	,
		SCHDEX
	)		const &

F77_FUNC() [30/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_FUNC	(	schinx	,
		SCHINX
	)		const &

F77_FUNC() [31/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_FUNC	(	schshx	,
		SCHSHX
	)		const &

F77_FUNC() [32/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_FUNC	(	slu1up	,
		SLU1UP
	)		const &

F77_FUNC() [33/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT const F77_CMPLX const F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT const F77_DBLE const F77_DBLE F77_DBLE* F77_RET_T F77_FUNC	(	slup1up	,
		SLUP1UP
	)		const &

F77_FUNC() [34/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T F77_FUNC	(	sqr1up	,
		SQR1UP
	)		const &

F77_FUNC() [35/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_FUNC	(	sqrdec	,
		SQRDEC
	)		const &

F77_FUNC() [36/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_FUNC	(	sqrder	,
		SQRDER
	)		const &

F77_FUNC() [37/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T F77_FUNC	(	sqrinc	,
		SQRINC
	)		const &

F77_FUNC() [38/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T F77_FUNC	(	sqrinr	,
		SQRINR
	)		const &

F77_FUNC() [39/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_FUNC	(	sqrshc	,
		SQRSHC
	)		const &

F77_FUNC() [40/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_FUNC	(	zch1dn	,
		ZCH1DN
	)		const &

F77_FUNC() [41/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_FUNC	(	zch1up	,
		ZCH1UP
	)		const &

F77_FUNC() [42/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_FUNC	(	zchdex	,
		ZCHDEX
	)		const &

F77_FUNC() [43/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_FUNC	(	zchinx	,
		ZCHINX
	)		const &

F77_FUNC() [44/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_FUNC	(	zchshx	,
		ZCHSHX
	)		const &

F77_FUNC() [45/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_FUNC	(	zlu1up	,
		ZLU1UP
	)		const &

F77_FUNC() [46/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT const F77_CMPLX const F77_CMPLX F77_CMPLX* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT const F77_DBLE const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT const F77_REAL const F77_REAL F77_REAL* F77_RET_T F77_FUNC	(	zlup1up	,
		ZLUP1UP
	)		const &

F77_FUNC() [47/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T F77_FUNC	(	zqr1up	,
		ZQR1UP
	)		const &

F77_FUNC() [48/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_FUNC	(	zqrdec	,
		ZQRDEC
	)		const &

F77_FUNC() [49/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_FUNC	(	zqrder	,
		ZQRDER
	)		const &

F77_FUNC() [50/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T F77_FUNC	(	zqrinc	,
		ZQRINC
	)		const &

F77_FUNC() [51/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T F77_FUNC	(	zqrinr	,
		ZQRINR
	)		const &

F77_FUNC() [52/52]

F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT F77_DBLE F77_DBLE* F77_RET_T F77_REAL const F77_INT F77_REAL F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE F77_DBLE F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL F77_REAL F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_CMPLX F77_REAL* F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE* F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_REAL F77_REAL* F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT const F77_DBLE_CMPLX F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT const F77_INT const F77_INT F77_CMPLX F77_REAL* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT const F77_INT F77_DBLE* F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT const F77_INT const F77_INT F77_REAL* F77_RET_T F77_FUNC	(	zqrshc	,
		ZQRSHC
	)		const &